IObundle

With the demise of Moore's law, architecture is becoming more and more critical. The demand for processors, hardware accelerators and specialized designs is increasing. Our goal is to create, distribute and support alternative architectures using RISC-V CPUs, programmable hardware accelerators, and various custom hardware blocks. IObundle promotes IOb-SoC , an open-source and free of charge Verilog/C++ System on Chip template, comprising a size-optimized RISC-V processor, internal RAM system with boot loading support, and a configurable cache system with L1 instruction/data caches plus a shared L2 cache. IObundle also promotes IOb-Versat , another open-source and free of charge Verilog/C++ SIP. IOb-Versat is a Coarse-Grained Reconfigurable Array for accelerating edge computing applications in an energy-efficient way. Our business model provides commercial IP cores and software using the above infrastructure and offers IP rights warranty, technical support, and customization design services to users of our infrastructure. Our IPs are verified using software models, RTL simulation and FPGA testing to provide a quality experience to our customers. José T. de Sousa